New Class of CMOS Chips To Address Quantum Computing Bottlenecks
ECE Associate Professor Cristian Cassella and Professor Marvin Onabajo are developing CMOS-based chips that are smaller and more energy efficient than current technology used to address quantum computing bottlenecks. High school students in Northeastern’s Young Scholars program will participate in this project.
This article originally appeared on Northeastern Global News. It was published by Cesareo Contreras. Main photo: Northeastern researchers Cristian Cassella and Marvin Onabajo work on low-power computer systems for complex problems. Photo by Matthew Modoono/Northeastern University
Northeastern engineers develop next-gen chips to tackle quantum computing’s biggest bottlenecks
Almost every major industry has them—challenges that cause bottlenecks in day-to-day operations. Think of a scientist working in biotechnology developing drugs, a manager of a cold supply chain operation looking to improve the routes of delivery trucks, or a financial broker trying to maximize their investments.
In quantum computing, these challenges can be framed as quadratic unconstrained binary optimization (QUBO) problems, which are solved using a range of technologies, including machine learning algorithms.
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These new chips will be designed to be ten times more efficient than current options. Photos by Matthew Modoono/Northeastern University |
Yet, one of the major computing systems used to handle these tasks—known as oscillator Ising machines (OIMs)—has some major downsides, explains Crisitan Cassella, a Northeastern University professor of electrical and computer engineering.
For one, they aren’t the most efficient in terms of computational power. Second, they aren’t very good at actually solving these problems at a fundamental architectural level, Cassella explains. Third, they aren’t easy to gain access to and can be costly.
Read full story at Northeastern Global News